In a semiconductor fabrication line, wafers and chips will inevitably be misprocessed or affected by defects as they move along hundreds of process steps. Many in-line tests are conducted and measurements taken, including defect inspection, metrology, parametric, and functional tests that monitor the health of wafers as they move down the fabrication line. Based on the results of these in-line tests/measurements, decisions may be made as to whether to dispose of potentially bad wafers. When wafers are found to be ‘really’ defective, i.e., having a high concentration of bad chips, these wafers will be discarded early in the process flow.
When a wafer is not disposed of based on existing wafer disposition criteria because, for example, there still remains a significant number of good chips on the wafer, some chips on the wafer may nonetheless be identified as bad chips through in-line testing. In other words, those wafers may have a mixture of potentially good and known bad chips and, therefore, may not be disposed of due to cost and/or economic considerations. However, chips that are known to be bad may continue to be subjected to subsequent in-line tests alongside with other good chips on the wafer. This presents several disadvantages: firstly, redundant testing of known bad chips wastes valuable testing time and resources. Secondly, the data collected on the bad chips confounds future data and yield analysis. Thirdly, by not disposing of the bad chips early in the fabrication process, there is a potential for the chips to escape wafer final test, causing a decreased shipped product quality level (SPQL).
The concept of adaptive testing has been known in the art as, for instance, in the article “Adaptive test adds value to wafer probe” authored by B. Bischoff et al. and published in Semiconductor International Magazine (August 2004) that provides a review of this area. Nevertheless, this article merely points to a general direction but fails short in providing any specific method to select which die to test or not to test. Generally, due to the high cost associated with in-line testing, only a very small portion of the chips on a wafer or in a lot are typically tested (approximately, 5% to 15% of all the chips). Therefore, without any specific instructions, it is not evident how chips are to be selected when most of the chips are not tested. Moreover, for the small portion of the chips that are tested, it is not clear how good chips may be separated from the bad chips unless criteria for judging good and bad are clearly established that correlates well with results obtained when performing wafer final testing.
U.S. Patent Application Publication No. 2004/0236531A1, titled “Method for Adaptively Testing Circuits Based on Parametric Fabrication Data” describes a method for adaptively changing the test content based on the results of in-line tests and in-line defect inspection. In this patent application, in-line testing or defect inspection is used to estimate process capability that determines whether the wafers/lots are healthy or poor. Based on the estimated process capability, the test program is modified, retaining only the parametric and functional tests needed for performance verification.
U.S. Patent Application Publication No. 2004/0181717A1 titled “Adaptive Defect Based Testing”, describes an adaptive testing method wherein the results of testing at a preceding stage are used to modulate the level of testing at a following stage. After each stage, a tested chip is partitioned into several bins, based in part on the logical structure of the integrated structure, and a defectivity value is assigned to each bin. Based on the assumption that bins having lower defectivity values contain relatively healthy chips, these chips are tested with a modified test—one having a lower level of testing, that is, with some tests being skipped. Conversely, bins tagged having higher defectivity values are tested with the full suite, or higher level (cycle) of testing.
Referring now to FIG. 1, a simplified flow chart is illustrated showing commonly practiced tests and measurements. For illustrative purposes, three test groups 1, 2, and 3 are depicted, each consisting of a group of tests and measurements typical of selected levels of in-line testing, (i.e., when the wafers are still in a clean room or early fabrication stages between process steps). A person skilled in the art will appreciate that additional steps may exist between steps illustrated in FIG. 1. Step 100 refers to a first step where wafers are brought into a clean room environment for processing. Step 101 is a test group labeled test group 1 representing a first test cycle. An example of such test group is CD (critical dimension) metrology for polysilicon gate, where the line width of polysilicon lines in a number of selected locations across the wafer is measured. Step 102 is another test group labeled test group 2, representing another test cycle. An example of such test group is transistor threshold voltage measurement, where the threshold voltage of a number of selected transistors across the wafer is measured. Step 103 is a test group labeled test group 3 representing a third test cycle. An example of such test group is the measurement of some specifically designed yield monitoring test structures across the wafer, for example, test structures monitoring metal-line-to-metal-line shorts. Other examples of test groups not listed may include optical and electron-beam-based inspection of circuit patterns to detect defects or systematic patterning failures as well as other various tests and measurements of other integrated circuits characteristics. Step 104 is the final step of the wafer in the fabrication flow. In this step, referenced as final product test, the product circuits on the wafer are tested. Typically, hundreds of process steps may exist between the first step 100, and the final step 104 in any semiconductor fabrication process flow.